Senior ASIC Design Engineer - DSP/Analog/SerDes
EmployerCelero Communications, Inc.
LocationIrvine, CA
Pay$150,000 – $250,000 per year
Posted2026-10-21
Confirmed open2026-11-01
Apply on the employer’s site Open in Atlas
About this role
Senior ASIC Design Engineer Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team…
Excerpt only. The full posting is on the employer’s careers site.
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